Critical-to-Off Interrupt Implementation (Windows Embedded CE 6.0)
1/6/2010
To implement the critical-to-off transition, implement a voltage comparator that generates a nonmaskable interrupt (NMI).
The following example demonstrates a possible implementation for an NMI interrupt service routine (ISR) function. This ISR should verify that there is a critically low battery condition, power down all peripherals as quickly as possible, place the RAM in the self-refresh state, and suspend the microprocessor. If the microprocessor continues from the suspend power state after the wake-up event, it needs to jump to the reset vector code.
The following example shows the microprocessor startup code that should run when the microprocessor is reset. It the last item to be run by the OS and may not be supported by all processors.
NmiISR Example
Use the following procedure to set up an NMI ISR:
- Mask NMI.
- Keep NMI from occurring
- Make sure there is truly a low battery condition.
- Power off all peripherals.
- Put RAM in self-refresh.
- Suspend the CPU.
- Jump reset vector.
- For CPUs that would continue after the wake-up, set a condition.
On x86 hardware, the kernel exports the OEMNMIHandler function, which OEMs can use to capture critical events in the system.
Some OEMs may have critical suspends handled by Power Manager in an interrupt service thread (IST) rather than in an ISR. To enable this, the critical power NMI could schedule a high priority IST that calls SetSystemPowerState. When it handles this system call, Power Manager can gracefully shut down critical devices and transfer power to other devices. It then puts the system into its lowest power mode with dynamic RAM (DRAM) refresh enabled. This approach requires that the hardware keep the system alive long enough for Power Manager to shut down processing.