PCI_COMMON_CONFIG (Windows CE 5.0)

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This structure describes the PCI configuration space for PCI devices.

typedef struct _PCI_COMMON_CONFIG {USHORT VendorID; USHORT DeviceID; USHORT Command; USHORT Status;UCHAR RevisionID; UCHAR ProgIf; UCHAR SubClass; UCHAR BaseClass; UCHAR CacheLineSize; UCHAR LatencyTimer; UCHAR HeaderType; UCHAR BIST;  union {    struct _PCI_HEADER_TYPE_0 {      ULONG BaseAddresses[PCI_TYPE0_ADDRESSES];      ULONG CIS;      USHORT SubVendorID;USHORT SubSystemID;ULONG ROMBaseAddress;ULONG Reserved2[2];UCHAR InterruptLine; UCHAR InterruptPin; UCHAR MinimumGrant; UCHAR MaximumLatency; } type0;struct _PCI_HEADER_TYPE_1 {   ULONG BaseAddresses[PCI_TYPE1_ADDRESSES]; UCHAR PrimaryBusNumber;    UCHAR SecondaryBusNumber;  UCHAR SubordinateBusNumber;UCHAR SecondaryLatencyTimer;    UCHAR IOBase;  UCHAR IOLimit;USHORT SecondaryStatus;    USHORT MemoryBase;  USHORT MemoryLimit;USHORT PrefetchableMemoryBase;    USHORT PrefetchableMemoryLimit;  ULONG PrefetchableMemoryBaseUpper32;ULONG PrefetchableMemoryLimitUpper32;    USHORT IOBaseUpper;  USHORT IOLimitUpper;ULONG Reserved2;    ULONG ExpansionROMBase;  UCHAR InterruptLine;UCHAR InterruptPin; USHORT BridgeControl;} type1;struct _PCI_HEADER_TYPE_2 {    ULONG BaseAddress;  UCHAR CapabilitiesPtr;UCHAR Reserved2;    USHORT SecondaryStatus;  UCHAR PrimaryBusNumber;UCHAR CardbusBusNumber;    UCHAR SubordinateBusNumber;  UCHAR CardbusLatencyTimer;ULONG MemoryBase0;    ULONG MemoryLimit0;  ULONG MemoryBase1;ULONG MemoryLimit1;    USHORT IOBase0_LO;    USHORT IOBase0_HI;  USHORT IOLimit0_LO;USHORT IOLimit0_HI;    USHORT IOBase1_LO;  USHORT IOBase1_HI;USHORT IOLimit1_LO;    USHORT IOLimit1_HI;  UCHAR InterruptLine;UCHAR InterruptPin;    USHORT BridgeControl;  USHORT SubVendorID;USHORT SubSystemID;    ULONG LegacyBaseAddress;  UCHAR Reserved3[56];ULONG SystemControl;    UCHAR MultiMediaControl;  UCHAR GeneralStatus;UCHAR Reserved4[2];    UCHAR GPIO0Control;  UCHAR GPIO1Control;UCHAR GPIO2Control;    UCHAR GPIO3Control;  ULONG IRQMuxRouting;UCHAR RetryStatus;    UCHAR CardControl;  UCHAR DeviceControl;UCHAR Diagnostic;} type2;} u;  UCHAR DeviceSpecific[108];} PCI_COMMON_CONFIG , *PPCI_COMMON_CONFIG;

Members

• VendorID
  PCI vendor identifier register.

• DeviceID
  PCI device identifier register.

• Command
  PCI command register.

• Status
  PCI status register.

• RevisionID
  PCI revision identifier register.

• ProgIf
  PCI programming interface register.

• SubClass
  PCI device sub-class register.

• BaseClass
  PCI device base-class register.

• CacheLineSize
  PCI cache line size register.

• LatencyTimer
  PCI latency timer register.

• HeaderType
  PCI header type register.

  The following table shows possible values.

  Value	Description
  0	Indicates a typical PCI device.
  1	Indicates a PCI-PCI bridge.
  2	Indicates a PCI-CardBus bridge.

• BIST
  PCI built-in self-test register.

• u.type0.BaseAddresses
  Array of PCI base address registers. Typical PCI devices have six base address registers, PCI-to-PCI bridges have two, and PCI-to-CardBus bridges have one.

• u.type0.CIS
  CardBus card information structure (CIS) pointer register.

• u.type0.SubVendorID
  PCI subsystem vendor identifier register.

• u.type0.SubSystemID
  PCI subsystem identifier register.

• u.type0.ROMBaseAddress
  PCI ROM base address register.

• u.type0.Reserved2
  Reserved.

• u.type0.InterruptLine
  PCI interrupt line register.

• u.type0.InterruptPin
  PCI interrupt pin register.

• u.type0.MinimumGrant
  PCI minimum grant register.

• u.type0.MaximumLatency
  PCI maximum latency register.

• u.type1.BaseAddress
  PCI base address register.

• u.type1.PrimaryBusNumber
  PCI primary bus number register.

• u.type1.SecondaryBusNumber
  PCI secondary bus number register.

• u.type1.SubordinateBusNumber
  PCI subordinate bus number.

• u.type1.SecondaryLatencyTimer
  PCI secondary latency timer.

• u.type1.IOBase
  Lower 8 bits of PCI I/O base address register.

• u.type1.IOLimit
  Lower 8 bits of PCI I/O limit address register.

• u.type1.SecondaryStatus
  PCI secondary status register.

• u.type1.MemoryBase
  PCI memory base address register.

• u.type1.MemoryLimit
  PCI memory limit address register

• u.type1.PrefetchableMemoryBase
  Lower 16 bits of PCI prefetchable memory base address register.

• u.type1.PrefetchableMemoryLimit
  Lower 16 bits of PCI prefetchable memory limit address register.

• u.type1.PrefetchableMemoryBaseUpper32
  Upper 32 bits of PCI prefetchable memory base address register.

• u.type1.PrefetchableMemoryLimitUpper32
  Upper 32 bits of PCI prefetchable memory limit address register.

• u.type1.IOBaseUpper
  Upper 16 bits of PCI I/O base address register.

• u.type1.IOLimitUpper
  Upper 16 bits of PCI I/O limit address register.

• u.type1.Reserved2
  Reserved.

• u.type1.ExpansionROMBase
  PCI expansion ROM base address register.

• u.type1.InterruptLine
  PCI interrupt line register.

• u.type1.InterruptPin
  PCI interrupt pin register.

• u.type1.BridgeControl
  PCI bridge control register.

• u.type1.BaseAddress
  PCI base address register.

• u.type2.CapabilitiesPtr
  PCI capabilities pointer register.

• u.type2.Reserved2
  Reserved.

• u.type2.PrimaryBusNumber
  PCI primary bus number register.

• u.type2.SecondaryStatus
  PCI secondary status register.

• u.type2.CardbusBusNumber
  CardBus bus number register.

• u.type2.SubordinateBusNumber
  PCI subordinate bus number.

• u.type2.CardbusLatencyTimer
  CardBus latency timer register.

• u.type2.MemoryBase0
  CardBus memory base address register 0.

• u.type2.MemoryLimit0
  CardBus memory limit address register 0.

• u.type2.MemoryBase1
  CardBus memory base address register 1.

• u.type2.MemoryLimit1
  CardBus memory limit address register 1.

• u.type2.IOBase0_LO
  Lower 16 bits of CardBus I/O base address register 0.

• u.type2.IOBase0_HI
  Upper 16 bits of CardBus I/O base address register 0.

• u.type2.IOLimit0_LO
  Lower 16 bits of CardBus I/O limit address register 0.

• u.type2.IOLimit0_HI
  Upper 16 bits of CardBus I/O limit address register 0.

• u.type2.IOBase1_LO
  Lower 16 bits of CardBus I/O base address register 1.

• u.type2.IOBase1_HI
  Upper 16 bits of CardBus I/O base address register 1.

• u.type2.IOLimit1_LO
  Lower 16 bits of CardBus I/O limit address register 1.

• u.type2.IOLimit1_HI
  Upper 16 bits of CardBus I/O limit address register 1.

• u.type2.InterruptLine
  PCI interrupt line register.

• u.type2.InterruptPin
  PCI interrupt pin register.

• u.type2.BridgeControl
  PCI bridge control register.

• u.type2.SubVendorID
  PCI subsystem vendor identifier register.

• u.type2.SubSystemID
  PCI subsystem identifier register.

• u.type2.LegacyBaseAddress
  CardBus legacy base address register.

• u.type2.Reserved3
  Reserved.

• u.type2.SystemControl
  CardBus system control register.

• u.type2.MultiMediaControl
  CardBus multimedia control register.

• u.type2.GeneralStatus
  CardBus general status register.

• u.type2.Reserved4
  Reserved.

• u.type2.GPIO0Control
  CardBus GPIO control registers.

• u.type2.GPIO1Control
  CardBus GPIO control registers.

• u.type2.GPIO2Control
  CardBus GPIO control registers.

• u.type2.GPIO3Control
  CardBus GPIO control registers.

• u.type2.IRQMuxRouting
  CardBus IRQ multiplexer routing register.

• u.type2.RetryStatus
  CardBus retry status register.

• u.type2.CardControl
  CardBus card control register.

• u.type2.DeviceControl
  CardBus device control register.

• u.type2.Diagnostic
  CardBus diagnostic register.

• DeviceSpecific
  Device specific registers in the PCI configuration space, varies by device.

Remarks

All PCI devices have a common set of registers that include VendorID, DeviceID, and so on.

This structure differs for these PCI devices: header type 0 for devices, header type 1 for PCI-to-PCI bridges, and header type 2 for PCI-to-CardBus bridges. For more information, see the PCI Local Bus Specification, revision 2.1 or 2.2.

Requirements

OS Versions: Windows CE .NET 4.0 and later.
Header: Ceddk.h.

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