Exceptions (AMD Intrinsics)
Microsoft Specific
The following table contains a list of exceptions that 3DNow! and MMX instructions can generate.
3DNow! and MMX Instruction Exceptions
| Exception | Real | Virtual 8086 | Protected | Description |
|---|---|---|---|---|
Invalid opcode (6) |
Yes |
Yes |
Yes |
The emulate instruction bit (EM) of the control register (CR0) is set to 1. |
Device not available (7) |
Yes |
Yes |
Yes |
Save the floating-point or MMX state if the task switch bit (TS) of the control register (CR0) is set to 1. |
Stack exception (12) |
Yes |
Yes |
Yes |
During instruction execution, the stack segment limit was exceeded. |
General protection (13) |
No |
No |
Yes |
During instruction execution, the effective address of one of the segment registers used for the operand points to an illegal memory location. |
Segment overrun (13) |
Yes |
Yes |
No |
One of the instruction data operands falls outside the address range 00000h to 0FFFFh. |
Page fault (14) |
No |
Yes |
Yes |
A page fault resulted from the execution of the instruction. |
Floating-point exception pending (16) |
Yes |
Yes |
Yes |
An exception is pending because of the floating-point execution unit. |
Alignment check (17) |
No |
Yes |
Yes |
An unaligned memory reference resulted from the instruction execution, and the alignment mask bit (AM) of the control register (CR0) is set to 1. (In Protected Mode, CPL = 3.) |
The rules for exceptions are the same for both MMX and 3DNow! instructions. In addition, exception detection and handling is identical for MMX and 3DNow! instructions. Exception handlers do not need modification.
An invalid opcode exception (interrupt 6) occurs if a 3DNow! instruction is executed on a processor that does not support 3DNow! instructions.
If a floating-point exception is pending and the processor encounters a 3DNow! instruction, FERR# is asserted and, if CR0.NE = 1, an interrupt 16 is generated. This is the same for MMX instructions.