Critical-to-Off Interrupt Implementation (Windows CE 5.0)
To implement the critical-to-off transition, implement a voltage comparator that generates a nonmaskable interrupt (NMI).
The following code example demonstrates a possible implementation for an NMI interrupt service routine (ISR) function. This ISR should verify that there is a critically low battery condition, power down all peripherals as quickly as possible, place the RAM in the self-refresh state, and suspend the microprocessor. If the microprocessor continues from the suspend power state after the wake-up event, it needs to jump to the reset vector code. The following code example shows the microprocessor startup code that should execute when the microprocessor is reset. The following code example will be the last item to get executed by the operating system and may not be supported by all processors.
NmiISR:
Mask NMI ; Keep NMI from occurring
; Make sure there is truly a low battery condition
for (i=0; i < 10; i++) {
Check Battery Level
If (Battery Level == OK) {
return SYSINTR_NOP;
}
}
Power off all peripherals
Put RAM in self refresh
Suspend CPU
Jump reset vector ; For CPUs that would continue after the wake-up
; condition
In the x86 hardware platform, the kernel exports the OEMNMIHandler function, which the OEM can use to capture critical events in the system.
Some OEMs may choose to have critical suspends handled by the Power Manager in an interrupt service thread (IST) rather than in an ISR. To enable this, the critical power NMI could schedule a high priority IST that calls SetSystemPowerState. When it handles this system call, the Power Manager can gracefully shut down critical devices and transfer power to other devices. It then puts the system into its lowest power mode with dynamic RAM (DRAM) refresh enabled. This approach would require that the platform hardware keep the system alive long enough for the Power Manager to shut down processing.
See Also
Send Feedback on this topic to the authors