Share via


SHx Microprocessor (Windows Embedded CE 6.0)

1/5/2010

All SHx interrupt service routines (ISRs) can be written in C. Any volatile registers can be used in accordance with the C calling convention without using save/restore. Specifically, an SHx ISR can use registers r0 through r7.

Use the following design principals when creating an OAL for an SHx microprocessor:

  • The ISR must return by means of rts, and cannot access any addresses through the translation look-aside buffer (TLB).
  • Implement the nonmaskable-interrupt ISR, OEMNMI.
  • OEMInit must register OEMNMI.
  • **

Nested interrupts.
The SHx kernel utilizes a structure that provides the kernel with information about which nested interrupts are masked while the current interrupt is being handled. To gain access to this structure, the IntrPriority global variable must be declared in the OAL.

See Also

Tasks

How to Develop an OEM Adaptation Layer

Concepts

Microprocessor-specific Issues