PCI_COMMON_CONFIG structure
The PCI_COMMON_CONFIG structure reports configuration data for a PCI device.
Syntax
typedef struct _PCI_COMMON_CONFIG {
USHORT VendorID;
USHORT DeviceID;
USHORT Command;
USHORT Status;
UCHAR RevisionID;
UCHAR ProgIf;
UCHAR SubClass;
UCHAR BaseClass;
UCHAR CacheLineSize;
UCHAR LatencyTimer;
UCHAR HeaderType;
UCHAR BIST;
union {
struct {
ULONG BaseAddresses[PCI_TYPE0_ADDRESSES];
ULONG Reserved1[2];
ULONG ROMBaseAddress;
ULONG Reserved2[2];
UCHAR InterruptLine;
UCHAR InterruptPin;
UCHAR MinimumGrant;
UCHAR MaximumLatency;
} type0;
} u;
UCHAR DeviceSpecific[192];
} PCI_COMMON_CONFIG, *PPCI_COMMON_CONFIG;
Members
VendorID
Contains an integer identifier, assigned by the PCI Special Interest Group (PSIG) that identifies the vendor of the device.DeviceID
Contains an integer identifier, assigned by the vendor, that identifies the device.Command
Contains the contents of the device's command register. The command register governs the behavior of the bridge. For an explanation of the contents of a PCI device's command register, see the PCI Local Bus Specification.Status
Contains the contents of the device's status register. For an explanation of the contents of a PCI device's status register, see the PCI Local Bus Specification.RevisionID
Contains an integer value, allocated by the vendor, that specifies a device-specific revision identifier.ProgIf
Contains a value, taken from the device's class code register, that indicates the device's programming interface. For an explanation of the contents of the class code register, see the PCI Local Bus Specification.SubClass
Contains a value, taken from the device's class code register, that indicates the device's subclass code. For an explanation of the contents of the class code register, see the PCI Local Bus Specification.BaseClass
Contains a value, taken from the device's class code register, that indicates the device's bass class. For an explanation of the contents of the class code register, see the PCI Local Bus Specification.CacheLineSize
Reports the contents of the device's cacheline register. For an explanation of the contents of the cacheline register, see the PCI Local Bus Specification.LatencyTimer
Reports the contents of the device's latency timer register. For more information about the contents of the latency timer register, see the PCI-to-PCI Bridge Architecture Specification.HeaderType
Reports the contents of the device's header type register. This register indicates the layout of data between bytes 0x010 to 0x03f in the device's configuration space. For more information about the contents of the header type register, see the PCI-to-PCI Bridge Architecture Specification.BIST
Reports the contents of the built-in self test register. For more information about the contents of the built-in self test register, see the PCI Local Bus Specification and the PCI-to-PCI Bridge Architecture Specification.u
type0
BaseAddresses
Reports the contents of base address registers for a type 0 device. These registers map internal device registers to a range of system addresses. For more information about the contents of the device base registers, see the PCI Local Bus Specification.Reserved1
Reserved.ROMBaseAddress
Reports the address of the expansion ROM, for PCI devices that implement an expansion ROM by means of an on-board EPROM. For more information about the expansion ROM address, see the PCI Local Bus Specification.Reserved2
Reserved.InterruptLine
Reports the line routing information retrieved from the interrupt line register. For more information about the contents of the interrupt line register, see the PCI Local Bus Specification.InterruptPin
Contains information from the interrupt pin register that indicates which interrupt pin the device uses. For more information about the contents of the interrupt pin register, see the PCI Local Bus Specification.MinimumGrant
Reports information from the MIN_GNT register that specifies how long a burst period the device needs assuming a clock rate of 33 MHz. For more information about the contents of the MIN_GNT register, see the PCI Local Bus Specification.MaximumLatency
Reports information from the MAX_LAT register that specifies how often the device needs to gain access to the PCI bus. For more information about the contents of the MAX_LAT register, see the PCI Local Bus Specification.
DeviceSpecific
Contains device specific information, not defined by the PCI standards bodies.
Remarks
The PCI_COMMON_CONFIG structure holds the configuration data returned by the IRP_MN_READ_CONFIG request.
Requirements
Header |
Wdm.h (include Wdm.h) |
See also