vs_3_0
A programmable vertex shader is made up of a set of instructions that operate on vertex data. Registers transfer data in and out of the ALU. Additional control can be applied to modify the instruction, the results, or what data gets written out.
Vertex shader version vs_3_0 extends the feature set supported by vs_2_x. Each of the features in vs_2_X that requires a cap to be set, is available in vs_3_0 without requiring the cap.
- Instructions - vs_3_0 contains a list of the available instructions.
- Registers - vs_3_0 lists the different types of registers used by the vertex shader ALU.
- Vertex Shader Register Modifiers are used to modify the way an instruction works.
- Vertex Shader Source Register Modifiers alter the source register data before the instruction runs.
- Source Register Swizzling gives additional control over which register components are read, copied, or written.
- Destination Register Masking determines what components of the destination register get written.
New Features
New features of vertex shader version vs_3_0 are listed in the following sections.
Indexing Registers
In the earlier shader models, only the constant register bank could be indexed. In this model, the following register banks can be indexed, using the loop counter register (aL):
- Input register (v#)
- Output register (o#)
Vertex Textures
This shader model supports texture lookup in the vertex shader using texldl. The vertex engine has four texture sampler stages (distinct from the displacement map sampler and the texture samplers in the pixel engine) that can be used to sample textures set at those stages. See Vertex Textures in vs_3_0 (DirectX HLSL).
Vertex Stream Frequency
This feature allows a subset of the input registers to be initialized at a rate different from once per vertex. See Drawing Non-Indexed Geometry.
Shader Output
Similar to vs_2_0, the output of the shader can vary with static flow control. Be careful with dynamic branching as this can cause shader outputs to vary per vertex. This will produce unpredictable results on different hardware.
Dynamic flow control
All dynamic flow control instructions are supported. The maximum nesting depth value allowed is 24. (See Flow Control Nesting Limits for details.)
Temporary Registers
A total of 32 temporary registers (r#) is supported.
Static Flow Control
The maximum nesting depth for loop - vs/rep - vs is 4. The maximum nesting depth for call - vs/callnz bool - vs/callnz pred - vs is 4. For if bool - vs, the maximum nesting depth value allowed is 24. (See Flow Control Nesting Limits for details.)
Predication
Instruction predication is supported. Use setp_comp - vs to set the predicate register.
Instruction Count
Each vertex shader is allowed anywhere from 512 up to the number of slots in MaxVertexShader30InstructionSlots in D3DCAPS9. The number of instructions run can be much higher because of the loop/rep support; however, this is capped by MaxVShaderInstructionsExecuted in D3DCAPS9 which should be at least 0xFFFF.
Device Caps
If Vertex Shader 3_0 is supported, the following caps are supported in hardware (at a minimum):
| Cap | Capability |
|---|---|
| Shader caps |
|
| GuardBandLeft, GuardBandTop, GuardBandRight, GuardBandBottom | 8K |
| VertexShaderVersion | 3_0 |
| MaxVertexShaderConst | 256 |
| MaxVertexShader30InstructionSlots | 512 |
| Fog support | D3DPRASTERCAPS_FOGVERTEX |
| VertexTextureFilterCaps | |
| D3DDEVCAPS2_VERTEXELEMENTSCANSHARESTREAMOFFSET | Vertex elements in a vertex declaration can share the same stream offset. |
| Vertex formats |
|
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